Fabrication of channel wraparound gate structure for field-effect transistor

ABSTRACT

A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.13/042,973, flied Mar. 8, 2011, which is a continuation of U.S. patentapplication Ser. No. 11/240,440, filed Sep. 29, 2005, now U.S. Pat. No.7,915,167, issued Mar. 29, 2011, the entire contents of which are herebyincorporated by reference herein.

FIELD OF THE INVENTION

The invention is in the field of Field-Effect Transistors.

PRIOR ART AND RELATED ART

The continuing trend in the fabrication of complementarymetal-oxide-semiconductor (CMOS) transistors is to scale thetransistors. Examples of transistors having reduced bodies along withtri-gate structures are shown in US 2004/0036127. Other smalltransistors are delta-doped transistors fanned in lightly doped orundoped epitaxial layers grown on a heavily doped substrate. See, forinstance, “Metal Gate Transistor with Epitaxial Source and DrainRegions,” application Ser. No. 10/955,669, filed Sep. 29, 2004, assignedto the assignee of the present application.

The ability to continue scaling CMOS transistors to even smallergeometries is hindered by the off-state leakage current. Off-statecurrent reduces the switching efficiency and robs system power. This isparticularly significant in planar CMOS transistors, where substrateleakage paths account for most of the current flow in the off state.While three-dimensional structures such as tri-gates and fin-FETs aremore scalable, since they have more effective electrostatic control,there still remains a leakage path in the channel.

One structure for providing a more completely wrapped around gate isdescribed in “Nonplanar Semiconductor Device with Partially or FullyWrapped Around Gate Electrode and Methods of Fabrication,” U.S. patentapplication Ser. No. 10/607,769, filed Jun. 27, 2003.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional, elevation view of a silicon-on-insulator(SOI) substrate.

FIG. 2 is a perspective view of the structure of FIG. 1, after theformation of a silicon body, sometimes referred to as a fin.

FIG. 3 illustrates the structure of FIG. 2, after a dummy gate isfabricated and during a first ion implantation step.

FIG. 4 illustrates the structure of FIG. 3, after spacers are fabricatedand during a second ion implantation step.

FIG. 5 illustrates the structure of FIG. 4, after forming a dielectriclayer and after the removal of the dummy gate.

FIG. 6 is a cross-sectional, elevation view of the structure of FIG. 5through section line 6-6 of FIG. 5.

FIG. 7 illustrates the structure of FIG. 6 during an ion implantationstep.

FIG. 8 illustrates the structure of FIG. 7 after an etching step whichremoves the BOX under the channel region. This view is generally throughsection line 8-8 of FIG. 5.

FIG. 9 is an enlarged view of the region beneath the gate after theformation of a gate dielectric layer and a gate metal.

FIG. 10 is a cross-sectional, elevation view taken through the sameplane as FIG. 6, this view illustrates the formation of the gateencircling the entire channel region of a semiconductor body.

DETAILED DESCRIPTION

A process for fabricating CMOS field-effect transistors and theresultant transistors are described. In the following description,numerous specific details are set forth, such as specific dimensions andchemical regimes, in order to provide a thorough understanding of thepresent invention. It will be apparent to one skilled in the art thatthe present invention may be practiced without these specific details.In other instances, well-known processing steps, such as cleaning steps,are not described in detail, in order to not unnecessarily obscure thepresent invention, Also in the description below, the fabrication of asingle transistor is described. As will be appreciated in the typicalintegrated circuit, both n and p channel transistors are fabricated.

In one embodiment, transistors are fabricated on a buried oxide layer(BOX) 20 which is disposed on a silicon substrate 21 shown in FIG. 1.Transistor bodies are fabricated from a monocrystalline, silicon layer24 disposed on BOX 20. This silicon-on-insulation (SOI) substrate iswell-known in the semiconductor industry. By way of example, the SOIsubstrate is fabricated by bonding the oxide layer 20 and silicon layer24 onto the substrate 21, and then planarizing the layer 24 until it isrelatively thin. Other techniques are known for forming an SOI substrateeluding, for instance, the implantation of oxygen into a siliconsubstrate to form a buried oxide layer. Other semiconductor materials,other than silicon, may also be used such as gallium arsenide.

As will be seen, the BOX is seeded through ion implantation beneath thechannel region of a transistor to make the oxide more readily etchablethan the overlying, silicon body. An electrically inactive species isimplemented so as to not alter the electrical characteristics of thesemiconductor body. Then, after removal of the BOX beneath the channel,a gate insulator and gate are formed entirely around the channel.

Referring to FIG. 1, the layer 24 may be selectively ion implanted witha p type dopant in regions where n channel transistors are to befabricated, and with an type dopant in those regions where p channeldevices are to be fabricated. This is used to provide the relativelylight doping typically found in the channel regions of MOS devicesfabricated in a CMOS integrated circuit.

A protective oxide is disposed on the silicon layer 24 followed by thedeposition of a silicon nitride layer (both not shown). The nitridelayer acts as a hard mask to define silicon bodies such as the siliconbody 25 of FIG. 2. By way of example, the body 25 may have a height andwidth of 20-30 nm.

An oxide (not shown) which subsequently acts as an etchant stop isformed over body 25. A polysilicon layer is formed over the structure ofFIG. 2 and etched to define a dummy gate 30 which extends over the body25 as seen in FIG. 3. The region of the body 25 below the dummy gate 30,as will be seen, is the channel region in this replacement gate process.Once the. dummy gate 30 has been defined, phosphorous or arsenic may beimplanted into the body 25 for an n channel transistor, or boron for a pchannel transistor in alignment with the dummy gate, as illustrated bythe ion implantation 26. This ion implantation defines the tip orextension source and drain regions frequently used in CMOS transistors.

Now, a layer of silicon nitride is conformally deposited over thestructure of FIG. 3 to fabricate the spacers 38 shown in FIG. 4.Ordinary, well-known, anisotropic etching is used to fabricate thespacers. In one embodiment, a carbon-doped nitride, doped with 5-13%carbon concentration is used for the spacers. After the spacerformation, the main part of the source and drain regions are formedthrough ion implantation 35 shown in FIG. 4. For the n channeltransistor, arsenic or phosphorous is used with an implant dose of up to1×10¹⁹-1×10²⁰ atoms/cm³. A similar dose range of boron may be used for ap channel transistor.

Following the implantation of the main source and drain region, thesilicon body 25, to the extent that it extends beyond the spacers 38,receives a suicide or salicide layer 39 as is often done on exposedsilicon in field-effect transistors.

An annealing step to activate the source and drain dopant is used, alsocommonly used cleaning steps common in the fabrication of a field-effecttransistor are not shown.

A dielectric layer 40 is now conformally deposited over the structure ofFIG. 4, as shown in FIG. 5. This may comprise a silicon dioxide layerwhich will become an interlayer dielectric (ILD) in an integratedcircuit or a low-k ILD may be used. Alternatively, a sacrificialdielectric layer may be used. In any event, the layer 40 typically hasthe mechanical strength to withstand a planarization process such aschemical mechanical polishing (CMP) so that it may be polished levelwith the top of the spacers 38.

After the deposition and planarization of the dielectric layer 40, a wetetch is used to remove the dummy polysilicon gate 30, leaving theopening 45, as shown in FIG. 5. (A dummy gate oxide (not shown) may alsobe removed.) The cross-sectional view of FIG. 6, taken through sectionline 6-6 of FIG. 5, also shows the body 25. This view is a betterreference for the ion implantation of FIG. 7.

Referring to FIG. 7, the wafer having the structure of FIG. 6 is now ionimplanted at an angle of θ° relative to the normal of the wafer with thewafer at two different angles of rotation. These angles of rotation arein the plane of the wafer and are referred to below as the waferrotation angle. The angle between the normal to the wafer and the ionbeam is referred to below as the ion implantation angle θ.

First, for instance, the wafer is ion implanted at the angle θ with thewafer rotated to an angle of 90°. Then, implantation occurs again at theangle θ with the wafer rotated to an angle of 270°. The wafer rotationangles of 90° and 270°, shown in FIG. 2 are perpendicular to the body25. Since 90° and 270° are 180° apart, the net effect is the same asimplanting at ±θ, as shown in FIG. 7. The implanted ions are implantedinto the dielectric 40, in the exposed portions of the BOX 20, as wellas under the channel region of the body 25 and in the channel region ofbody 25. θ may be in the range of 30°-60°, the angle is selected so asto insure that the ions are implanted into all the BOX 20 under the body25.

Ions seeded into the upper portion of BOX 20, shown as region 20 a,cause BOX 20 to be more readily etched and to provide better selectivitybetween the region 20 a versus the body 25 and the non-implanted regionsof BOX. 20. The ions alter the crystalline nature of BOX 20, in effect,amorphizing or modifying the structure making it less resistant toselected chemistry without making body 25 or non-implanted regions ofthe BOX 20 more readily etched. More specifically, by selecting,suitable ions and a suitable wet etchant, the implanted region 20 a isetched more readily in the presence of the wet etchant compared to thebody 25 or unexposed portions of the BOX 20, allowing the implantedportion of the BOX 20 (region 20 a), including beneath the body 25 to beremoved without substantially affecting the dimensions of the body 25. Adiscussion of pre-etch implantation may be found in US2004/0118805. Wetetchant discrimination ratio of 6-1 between implanted silicon dioxideand non-implanted silicon dioxide are achievable.

Ions selected for the implantation shown in FIG. 7 are electricallyinactive in the BOX 20 and the semiconductor body 25. For example,silicon can be implanted where the body 25 is a silicon body, to disruptthe structure of the silicon dioxide without altering the electricalproperties of the body 25. In subsequent annealing, the additionalsilicon ions implanted in body 25 are re-crystallized and havesubstantially no impact on the transistor characteristics. Further,electrically inactive species such as nitrogen or halogens (fluorine,chlorine, etc.) may be implanted to create structural alteration withthe resultant modification of the wet etch rate without adverselyeffecting the electrical behavior of the transistor. These speciesremain in the silicon without altering the electrical characteristics ofthe transistor which is subsequently formed.

Relatively low implantation energies and dose levels are adequate tosufficiently seed the BOX 20 beneath the body 25 to allow removal of theoxide below the body. For example, energy levels for implanting siliconin the range of 0.5-2.0 KeV, to a dose of 1×10¹⁸ atoms/cm² aresufficient for a silicon body having dimensions of approximately 20×20nm.

Following the implantation, a wet etch is used to remove the region 20 aincluding the region 20 a under the body 25. Many wet chemical etchantsare known to be effective and controllable on such thin film materials.As would be apparent to one skilled in the art, they may beappropriately matched with substrate and thin film materials, such asthose above, to provide desirable selective etching. Suitable etchantsinclude but are not limited to phosphoric acid (H₃PO₄), hydrofluoricacid (HF), buffered HF, hydrochloric acid (HCl), nitric acid (HNO₃),acetic acid (CH₃COOH), ammonium hydroxide (NH₄OH, alcohols, potassiumpermanganate (KMnO₄), ammonium fluoride (NH₄F), and others, as would belisted in known Wet chemical etching references such as Thin FilmProcesses, Academic Press 1978), edited by John L. Vossen and WernerKern, Mixtures of these and other etchant chemicals are alsoconventionally used.

The wet etchant of the region 20 a of layer 20 defines a trench alignedwith the opening 45 which extends beneath the body 25. This trench isbest seen in FIG. 8 as trench 50. Note, this view is taken through thesection lines 8-8 of FIG. 5. In this view the source and drain regions55 are visible. The trench 50 is encircled with the circle 60, andenlarged in FIG. 9, as will be subsequently discussed.

A gate dielectric 62 may now be formed on exposed surfaces whichincludes the sides, top and bottom of the body 25, The gate dielectrichas a high dielectric constant (k), such as a metal oxide dielectric,for instance, HfO₂ or ZrO₂ or other high k dielectrics, such as PZT orBST. The gate dielectric may be formed by any well-known technique suchas atomic layer deposition (ALD) or chemical vapor deposition (CVD).Alternately, the gate dielectric may be a grown dielectric. Forinstance, the gate dielectric 62, may be a silicon dioxide film grownwith a wet or dry oxidation process to a thickness between 5-50 Å.

Following this a gate electrode (metal) layer 63 is formed over the gatedielectric layer 62. The gate electrode layer 62 may be formed byblanket deposition of a suitable gate electrode material. In oneembodiment a gate electrode material comprises a metal film such astungsten, tantalum, titanium and/or nitrides and alloys thereof. For then channel transistors, a work function in the range of 3.9 to 4.6 eV maybe used. For the p channel transistors, a work function of 4.6 to 5.2 eVmay be used. Accordingly, for substrates with both n channel and pchannel transistors, two separate metal deposition processes may need tobe used. Only approximately 100 Å of the metal needs to be formedthrough ALD to set the work function. The remainder of the gate may beformed of polysilicon.

Standard processing is now used to complete the transistor of FIG. 10.

The formation of the gate beneath the body 25 may not be as well definedas the gate on the sides and top of the body 25. For instance, as shownin FIG. 9, a void 64 may occur. Such a void, however, will not affectthe performance of the transistor. Moreover, some of the BOX 20 (notshown) may remain directly under the body 25 in the trench 50. Thisoxide, which is subsequently covered with both the high-k dielectric 62and the metal 63, will not meaningfully impact transistor performance.

The above described method may also be used cm other three dimensional(3D)) semiconductor bodies such as semiconducting carbon nanotubes,Group 3-5 nanowires and silicon nanowires. The surface upon which the 3Dsemiconductor nanostructure rests is ion implanted to alter its etchingrate to make it more etchable than the nanostructure.

Thus, a method has been described for forming a gate entirely around asilicon body in a replacement gate process. Ion implantation damages theinsulation beneath the semiconductor body in the channel region allowingit to be more readily etched. ALD is then used to form a dielectric andgate entirely around the semiconductor body for one embodiment.

What is claimed is:
 1. A semiconductor structure, comprising: asemiconductor body above a substrate, the semiconductor body having atop surface, a pair of sidewalls, and a bottom; a gate electrode hayinga first portion over a portion of the top surface of the semiconductorbody, a second portion adjacent a portion of the sidewalls of thesemiconductor body, and a third portion below the bottom surface of thesemiconductor body, wherein the first portion of the gate electrode iscontinuous with the second portion of the gate electrode, and whereinthe third portion of the gate electrode is continuous with the secondportion of the gate electrode; a gate dielectric layer between the firstportion of the gate electrode and the portion of the top surface of thesemiconductor body, between the second portion of the gate electrode andthe portion of the sidewalls of the semiconductor body, and between thethird portion of the gate electrode and the bottom surface of thesemiconductor body, Wherein is continuous around a top surface, sidewallsurfaces and a bottom surface of the third portion of the gateelectrode; an insulating layer above the substrate and laterallyadjacent to the third portion of the gate electrode; a source region ata first side of the gate electrode; and a drain region at a second sideof the gate electrode opposite the first side of the gate electrode. 2.The semiconductor structure of claim 1, wherein the insulating layer islaterally adjacent to a portion of the gate dielectric layer between thethird portion of the gate electrode and the bottom surface of thesemiconductor body.
 3. The semiconductor structure of claim 1, whereinthe third portion of the gate electrode comprises a void surrounded by atop portion, sidewall portions and a bottom portion of the third portionof the gate electrode.
 4. The semiconductor structure of claim 1,wherein the third portion of the gate electrode is void-free.
 5. Thesemiconductor structure of claim 1, wherein the gate dielectric layercomprises a high-k dielectric material.
 6. The semiconductor structureof claim 5, wherein the gate electrode comprises a metal and has a workfunction between 3.9 to 5.2 eV.
 7. The semiconductor structure of claim1, wherein the gate electrode comprises a metal and has a work functionbetween 3.9 to 5.2 eV.
 8. A method of fabricating a semiconductorstructure, the method comprising: forming a semiconductor body above asubstrate, the semiconductor body having a top surface, a pair ofsidewalls, and a bottom; forming a gate electrode having a first portionover a portion of the top surface of the semiconductor body, a secondportion adjacent a portion of the sidewalls of the semiconductor body,and a third portion below the bottom surface of the semiconductor body,wherein the first portion of the gate electrode is continuous with thesecond portion of the gate electrode, and wherein the third portion ofthe gate electrode is continuous with the second portion of the gateelectrode; forming a gate dielectric layer between the first portion ofthe gate electrode and the portion of the top surface of thesemiconductor body, between the second portion of the gate electrode andthe portion of the sidewalls of the semiconductor body, and between thethird portion of the gate electrode and the bottom surface of thesemiconductor body, wherein is continuous around a top surface, sidewallsurfaces and a bottom surface of the third portion of the gateelectrode; forming an insulating layer above the substrate and laterallyadjacent to the third portion of the gate electrode forming a sourceregion at a first side of the gate electrode; and forming a drain regionat a second side of the gate electrode opposite the first side of thegate electrode.
 9. The method of claim 8, wherein the insulating layeris laterally adjacent to a portion of the gate dielectric layer betweenthe third portion of the gate electrode and the bottom surface of thesemiconductor body.
 10. The method of claim 8, wherein the third portionof the gate electrode comprises a void surrounded by a top portion,sidewall portions and a bottom portion of the third portion of the gateelectrode.
 11. The method of claim 8, wherein the third portion of thegate electrode is void-free.
 12. The method of claim 8, wherein the gatedielectric layer comprises a high-k dielectric material.
 13. The methodof claim 12, wherein the gate electrode comprises a metal and has a workfunction between 3.9 to 5.2 eV.
 14. The method of claim 8, wherein thegate electrode comprises a metal and has a work function between 3.9 to5.2 eV.